Principal ASIC Design Engineer
Posted on Nov 5, 2020 by Fortinet
Work with architecture team to shape micro-architecture of next-generation SOC FortiASIC.
Work with IP teams to review verification test plan, coverage analysis and full-chip simulation.
Design implementation using Verilog HDL and synthesis.
Work with physical design teams to verify constraints, optimize place & route and achieve timing closure.
A self-starter with ability to manage time effectively and work within a diverse team environment.
Experienced in design and implementation of complex multi-million gate SOCs.
Familiarity with high speed IP protocols including SATA, eMMC, USB, PCIe and DDR.
Strong experience designing digital circuits using Verilog HDL.
Strong experience in formal verification of digital design.
Fluent in C, C++, assembly and Scripting languages.
Excellent communication skills.
MS & BS in Electrical Engineering or related field with 7+ years of SOC ASIC design experience.