Power Management IP Microarchitect/Designer
Posted on Apr 6, 2021 by Intel
Oversee definition, design, verification, and documentation for SoC (System on a Chip) development
Determine architecture design, logic design, and system simulation.
Define module interfaces/formats for simulation
Perform logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, register transfer level coding, and simulation for SoCs
Contribute to the development of multidimensional designs involving the layout of complex integrated circuits
Perform all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.
Analyze equipment to establish operation infrastructure, conduct experimental tests, and evaluate results
Review vendor capability to support development
In addition to the qualifications listed below, the ideal candidate will also demonstrate the following traits:
Highly proactive, self-motivated, result oriented and goal driven
Strong analytical and communication skills
Passionate, dynamic, self-driven and out-reaching
Willingness to work in highly cross-cultural, cross-disciplinary and cross-geographic locations
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Candidate must have a in Electrical or Computer Engineering and 9+ of industry - OR - a in Electrical or Computer Engineering and 6+ of industry .
7+ of in:
Design, Architecture and Microarchitecture phases of IP/SoC
Workload analysis, use case analysis performance and power optimizations, explorations and analysis.
Architectural modeling of power, performance characteristics of complex IPs and SoCs
ASIC design flow, EDA tools, Pre/Post Silicon validation process, low power methodologies
SoC architectures for Mobile and Computing devices and platforms
interacting and influencing software and driver/firmware developers to optimize PnP
HDL and SV based design and verification tools and flows
Working in cross-functional teams and root cause analysis
1+ of in:
CPU, DDR, IO systems, accelerators